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? 2003 tdk semiconductor corporation, proprietary and confidential rev_1.1 txd[3:0] 4b/5b encoder, scrambler, parallel/serial parallel/serial, manchester encoder manchester decoder, parallel/serial serial/parallel descrambler, 5b/4b decoder nrz/nrzi mlt3 encoder tx clk gen carrier sense, collision detect clk recovery clock reference 100m 10m 25mhz pulse shaper and filter a uto negotiation a daptive eq, baseline wander correct, mlt3 decode, nrzi/nrz leds ledl ledbtx ledtx ledcol ledbt ledfx ledrx mdi 10m 100m ckin ps gnd vcc mii registers & interface logic rxd[3:0] tx_clk rx_clk 4b/5b encoder, scrambler, parallel/serial parallel/serial, manchester encoder manchester decoder, parallel/serial serial/parallel descrambler, 5b/4b decoder nrz/nrzi mlt3 encoder tx clk gen carrier sense, collision detect clk recovery clock reference 100m 10m 25mhz pulse shaper and filter a uto negotiation a daptive eq, baseline wander correct, mlt3 decode, nrzi/nrz leds mdi 10m 100m rxip/n txop/n ps gnd vcc mii registers & interface logic 78Q2120C 10/100base-tx transceiver august 2003 description the 78Q2120C is a 10base-t/100base-tx fast ethernet transceiver. it in cludes integrated mii, endecs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation function. the transmitter includes an on-chip pulse-shaper and a low-power line driver. the receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. the transceiver interfaces to category-5 unshielded twisted pair (cat- 5 utp) cabling for 100base-tx/10base-t and category-3 unshielded tw isted pair for 10base-t, and is connected to the line media via 1:1 isolation transformers. no external filter is required. interface to the mac is accompli shed through an ieee-802.3 compliant media independent interface (mii). the product is fabricated in an advanced cmos process for high performance and low power operation. features ? 10base-t/100base-tx ieee-802.3 compliant tx and rx functions requiring a dual 1:1 isolation transformer interface to the line ? integrated mii, 10base-t/100base-tx endec, 100base-tx scrambler/descrambler, and full- featured auto-negotiation function ? full duplex operation capable ? pcs bypass supports 5-bit symbol interface ? register-programmable transmit amplitude ? dual speed digital clock recovery ? automatic polarity correction during auto- negotiation and 10base-t signal reception ? power-saving and power-down modes including transmitter disable ? led indicators: link, tx, rx, col, 100, 10, fdx ? user programmable interrupt pin ? 64-pin tqfp (jedec lqfp) package ? single 3.3 v 0.3v supply block diagram
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 2 - rev_1.1 functional description general power management the 78Q2120C has three power saving modes: ? chip power-down ? receive power management ? transmit high impedance mode chip power-down is activated by setting the pwrdn bit in the mii register (mr0.11) or pulling high the pwrdn pin. when the chip is in power-down mode, all on-chip circuitry is shut off, and the device consumes minimum power. while in power-down state, the 78Q2120C still responds to management transactions. receive power management (rxcc mode) is activated by setting the rxcc bit in the mii register (mr16.0). in this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (pll), and all other receive circuitry will be powered down when no valid mlt-3 signal is present at the utp receive line interface. as soon as a valid signal is detected, all circuits w ill automatically be powered up to resume normal operation. during this mode of operation, rx_clk will be inactive when there is no data being received. note that the rxcc mode is not supported during 10base-t operation. transmit high impedance mode is activated by setting the txhim bit in the mii register (mr16.12). in this mode of operation, the transmit utp drivers are in a high impedance state and tx_clk is tri- stated. a weak internal pull-up is enabled on tx_clk. the receive circuitry remains fully operational. the default state of mr16.12 is a logic low for disabling the transmit high impedance mode. the transmitter is fully functional when mr16.12 is cleared. analog biasing and supply regulation the 78Q2120C requires no external component to generate on-chip bias voltages and currents. high accuracy is maintained through a closed-loop trimmed biasing network. on-chip digital logic runs off an internal voltage regulator. hence only a single vcc supply is required to power-up the device. the on-chip regulator is not affected by power-down mode. clock selection the 78Q2120C will use the on-chip crystal oscillator as the clock source if the ckin pin is tied low. in this mode of operation, a 25mhz crystal should be connected between the xtlp and xtln pins. alternatively, an external 25mhz clock input can be connected to the ckin pin. the chip senses activity on the ckin pin, and will automatically configure itself to use the external clock, if present. in this mode of operation, a crystal is not required and the xtlp and xtln pins should be left floating or connected together. transmit clock generation the transmitter uses an on-chip frequency synthesizer to generate the transmit clock. in 100base-tx operation, the synthesizer multiplies the reference clock by 5 to obtain the internal 125mhz serial transmit clock. in 10base-t mode, it generates an internal 20mhz transmit clock by multiplying the reference 25mhz clock by 4/5. the synthesizer references eith er the local 25 mhz crystal oscillator, or the externally applied clock, depending on the selected mode of operation. receive signal qualification the integrated signal qualifier has separate squelch and unsquelch thresholds, and includes a built-in timer to ensure fast and accurate signal detection and line noise rejection. upon detection of two or more valid 10base-t or 100base-tx pulses on the line receive port, the pass signal, indicating the presence of valid receive signal or data, will be asserted. when pass is asserted, the signal detect threshold is lowered by about 60%, and all adaptive circuits are released from their initial states and allowed to lock onto the incoming data. in 100base-tx operation, pass will be de- asserted when no signal is presented for a period of about 1.2us. in 10base-t operation, pass will be de- asserted whenever no manchester data is received. in either case, the signal detect threshold will return to the squelched level whenever the pass indication is de- asserted. the pass signal is also used to control the operation of the clock/data recovery circuit to assure fast acquisition. receive clock recovery in 100base-tx mode, the 125mhz receive clock is extracted using a digital dll-based loop. when no receive signal is present, the dll is directed to lock onto the 125mhz transmit serial clock. when pass is asserted, the dll will use the received mlt-3 signal as the clock reference. the recovered clock is used to
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 3 - rev_1.1 re-time the data signal and for conversion of the data to nrz format. in 10base-t mode, the 10mhz receive clock is recovered digitally from the manchester data using a dll locked to the reference clock. when manchester-coded preambles are detected, the dll immediately re-aligns the phase of the clock to synchronize with the incoming data. hence clock acquisition is fast and immediate. 100base-tx operation 100base-tx transmit the 78Q2120C contains all of the necessary circuitry to convert the transmit mii signaling from a mac to an ieee-802.3 co mpliant data-stream driving cat-5 utp cabling. the internal pcs interface maps 4 bit nibbles from the mii to 5 bit code groups as defined in table 24-1 of ieee-802.3. these 5 bit code groups are then scrambled and converted to a serial stream before being sent to the mlt-3 pulse shaping circuitry and line driver. the pulse-shaper uses current modulation to produce the desired output waveform. controlled rise/fall time in mlt-3 signal is achieved using an accurately controlled voltage ramp generator. the line driver requires an external 1:1 isolation transformer to interface with the line media. the center-tap of the primary side of the transformer should be connected to the vcc supply. 100base-tx receive the 78Q2120C receives a 125mbaud mlt-3 signal through a 1:1 transformer. the signal then goes through a combination of adaptive offset adjustment (baseline wander correction) and adaptive equalization. the effect of these circuits is to sense the amount of dispersion and attenuation caused by the cable and transformer, and restore the received pulses to logic levels. the amount of gain and equalization applied to the pulses varies with the detected attenuation and dispersion and, therefore, with the length of the cable. the 78Q2120C can compensate for cable loss of up to 10db at 16 mhz. this loss is represented as test-chan 5 in annex a of the ansi x3.263:199x specification. the equalized mlt-3 data signal is bi-directionally sliced and the resulting nrzi bit-stream is presented to the cdr where it is re-timed and decoded to nrz format. the re-timed serial data is converted to parallel, then descrambled and aligned into 5 bit code groups. the receive pcs interface maps these code groups to 4 bit data for the mii as outlined in table 24-1 in clause 24 of ieee-802.3. pcs bypass mode (auto-negotiate must be off) the pcs bypass mode is entered by pulling pcsbp high or by setting register bit mr 16.1. in this mode the 78Q2120C accepts scrambled 5 bit code words into the pins tx_er and txd[3:0], tx_er being the msb of the data input. the 5 bit code groups are converted to mlt-3 signal for transmission. the received mlt-3 signal is converted to 5 bit nrz code groups and output from the rx_er and rxd[3:0] pins, rx_er being the msb of the data output. the rx_dv and tx_en pins are unused in pcs bypass mode. 10base-t operation 10base-t transmit the 78Q2120C takes 4 bit parallel nrz data via the mii interface and passes it through a parallel to serial converter. the data is then passed through a manchester encoder, pre-emphasis pulse-shaper, media filter, and finally to the twisted-pair line driver. the pulse-shaper and filter ensures the output waveforms meet the output voltage template and spectral content requirements detailed in clause 14 of ieee-802.3. interface to the twisted-pair media is through two external 50 ? resistors and a center- tapped 1:1 transformer. no external filtering is required. during auto-negotiation and 10base-t idle periods, link pulses are transmitted. the 78Q2120C employs an onboard timer to prevent the mac from capturing a network through excessively long transmissions. when this timer expires, the chip enters the jabber state and transmission is halted. the jabber state is exited after the mii goes idle for 500 250ms. 10base-t receive the 78Q2120C receives manchester-encoded 10base-t data through the twisted pair inputs and re-establishes logic levels through a slicer with a smart squelch function. the slicer automatically adjusts its level after valid data with the appropriate levels are detected. data is passed on to the cru where the clock is recovered, and the data is re- timed and decoded. from there, data enters the serial-to-parallel converter for transmission to the mac via the media independent interface. interface to the twisted-pair media is through an external 100 ? shunt resistor and a 1:1 transformer. polarity information is detected and corrected within internal circuitry.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 4 - rev_1.1 polarity correction the 78Q2120C is capable of either automatic or manual polarity reversal for 10base-t and auto- negotiation functions. register bits mr16.5 and mr16.4 control this feature. the default is automatic mode where mr16.5 is low and mr16.4 indicates if the detection circuitry has inverted the input signal. to enter manual mode, mr16.5 should be set high and mr16.4 will then control the signal polarity. sqe test the 78Q2120C supports the signal quality error (sqe) function detailed in ieee-802.3. at an interval of 1 s after each negative transition of the txen pin in 10base-t mode, the col pin will go high for a period of 1 s. this function can be disabled through register bit mr16.11. natural loopback when enabled, whenever the 78Q2120C is transmitting and not receiving on the twisted pair media (10base-t half dupl ex mode), data on the txd[3:0] pins is looped back onto the rxd[3:0] pins. during a collision, data from the rxi pins is routed to the rxd[3:0] pins. the natural loopback function is enabled through register bit mr16.10. repeater mode when the rptr pin is high or register bit mr16.15 is set, the 78Q2120C is placed in repeater mode. in this mode, full duplex operation is prohibited, crs responds only to receive activity and, in 10base-t mode, the sqe test function is disabled. auto-negotiation the 78Q2120C supports the auto-negotiation functions of clause 28 of ieee-802.3. this function can be enabled via a pin selection or register settings. if the anega pin is tied high, the auto- negotiation function defaults to on and bit mr0.12 (anegen) is high after reset. software can disable the auto-negotiation function by writing to bit mr0.12. if the anega pin is tied low, the function defaults to off and bit mr0.12 is set low after reset and cannot be written to. the contents of register mr4 are sent to the 78Q2120C?s link partner during auto-negotiation, coded in fast link pulses. bits mr4.8:5 reflect the state of the tech[2:0] pins after reset. if tech[2:0] = ?111?, then all 4 bits are high. if tech[2:0] = ?001?, then only bit 5 is high. after reset, software can change any of these bits from a ?1? to a ?0?; but not from a ?0? to a ?1?. therefore, a technology permitted by the setting of the tech pins can be disabled, but cannot be enabled through register selection. with auto-negotiation enabled, the 78Q2120C will start sending fast link pulses at power on, loss of link or a command to restart. at the same time, it will look for either 10base-t id le, 100base-tx idle, or fast link pulses from its link partner. if either idle pattern is detected, the 78Q2120C configures itself in half-duplex mode at the appropriate speed. if it detects fast link pulses, it decodes and analyzes the link code transmitted by the link partner. when three identical link code words are received (ignoring the acknowledge bit) the link code word is stored in register mr5. upon receiving three more identical link code words, with the acknowledge bit set, the 78Q2120C configures itself to the highest priority technology common to the two link partners. the technology priorities are, in descending order: 100base-tx, full duplex 100base-tx, half duplex 10base-t, full duplex 10base-t, half duplex once auto-negotiation is complete, register bits mr18.11:10 will reflect the actual speed and duplex that was chosen. if auto-negotiation fails to establish a link for any reason, register bit mr18.12 will reflect this and auto negotiation will restart from the beginning. writing a ?1? to bit mr0.9(raneg) will also cause auto- negotiation to restart. media independent interface mii transmit and receive operation the mii interface on the 78Q2120C provides independent transmit and receive paths for both 10mb/s and 100mb/s data rates as described in clause 22 of the ieee-802.3 standard. the transmit clock, tx_clk, provides the timing reference for the transfer of tx_en, txd[3:0], and tx_er signals from the mac to the 78Q2120C. txd[3:0] is captured on the rising edge of tx_clk when tx_en is asserted. tx_er is also captured on the rising edge of tx_clk and is asserted by the mac to request that an error code group be transmitted. the assertion of tx_er has no affect when the 78Q2120C is operating in 10base-t mode. the receive clock, rx_clk, provides the timing reference to transfer rx_dv, rxd[3:0], and rx_er signals from the 78Q2120C to the mac. rx_dv
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 5 - rev_1.1 transitions synchronously with respect to rx_clk and is asserted when the 78Q2120C is presenting valid data on rxd[3:0]. rx_er is asserted when a code group violation has been detected in the current receive packet and is also synchronous to rx_clk. station management interface the station management interface consists of circuitry which implements the serial protocol as described in clause 22.2.4.5 of ieee-802.3. a 16- bit shift register receives serial data applied to the mdio pin at the rising-edge of the mdc clock signal. once the preamble is received, the station management control logic looks for the start-of- frame sequence and a read or write op-code, followed by the phyad and regad fields. for a read operation, the mdio port becomes enabled as an output and the register data is loaded into a shift register for transmission. the 78Q2120C can work with a one bit preamble rather than the 32 bits proscribed by ieee-802.3. this allows for faster programming of the registers. if a register does not exist at an address indicated by the regad field or if the phyad field does not match the 78Q2120C phyad indicated by the phyad pins, a read of the mdio port will return all ones. for a write operation, the data is shifted in and loaded into the appropriate register after the sixteenth data bit has been received. when the phyad field is all zeros, the station management entity (sta) is requesting a broadcast data transaction. all phys sharing the same management interface must respond to this broadcast request. the 78Q2120C will respond to the broadcast data transaction. additional features led indicators there are seven led pins that can be used to indicate various states of operation of the 78Q2120C. there is an led pin that indicates the link is up ( ledl ), others that indicates the 78Q2120C is either transmitting ( ledtx ) or receiving ( ledrx ), one that signals a collision event ( ledcol ), two more that reflect the data rate ( ledbtx and ledbt ), and one that reflects full duplex mode of operation ( ledfdx ). interrupt pin the 78Q2120C has an interrupt pin (intr) that is asserted whenever any of the eight interrupt bits of mr17.7:0 are set. these interrupt bits can be disabled via mr17.15:8 interrupt enable bits. the interrupt level bit, mr16.14, controls the active level of the intr pin. when the intr pin is not asserted, the pin is held in a high impedance state.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 6 - rev_1.1 pin description legend type description type description a analog pin ci ttl-level input ciu ttl-level input w/ pull-up cid ttl-level input w/ pull-down cis ttl-level input w/ schmitt trigger cio ttl-compatible bi-directional pin co cmos output coz tristate-able cmos output s supply g ground mii (media independent interface) name pin type description tx_clk 27 coz transmit clock: tx_clk is a conti nuous clock, which provides a timing reference for the tx_en, tx_er and tx d[3:0] signals from the mac. the clock frequency is 25mhz in 100base -tx mode and 2. 5mhz in 10base-t mode. this pin is tristated in isolate mode and txhim mode. tx_en 28 ci transmit enable: tx_en is asserted by the mac to indicate that valid data for transmission is present on the txd[3:0] pins. txd[3:0] 32-29 ci transmit data: txd[3:0] receives dat a from the mac for transmission on a nibble basis. this data is capt ured on the rising edge of tx_clk when tx_en is high. tx_er 26 ci transmit error: tx_er is asserted hi gh to request that an error code- group be transmitted when tx_en is high. in pcs bypass mode this pin becomes the msb of the transmit 5-bit code group. crs 34 coz carrier sense: when the 78Q2120C is not in repeater mode, crs is high whenever a non-idle condition exists on either the transmitter or the receiver. in repeater mode, crs is only active when a non-idle condition exists on the receiver. this pin is tristated in isolate mode. col 33 coz collision: col is asserted high when a collision has been detected on the media. in 10base-t mode, col is also used for the sqe test function. this pin is tristated in isolate mode. rx_clk 24 coz receive clock: rx_clk is a conti nuous clock, which provides a timing reference to the mac for the rx_dv, rx_er and rxd[3:0] signals. the clock frequency is 25mhz in 100base- tx mode, and 2.5mhz in 10base-t mode. to reduce powe r consumption, in 100 base-tx mode, the 78Q2120C provides an optional mode, enabled through mr16.0, in which rx_clk is held inactive (low) when no receive data is detected. this pin is tristated in isolate mode. rx_dv 23 coz receive data valid: rx_dv is asserted high to indicate that valid data is present on the rxd[3:0] pins. in 100b ase-tx mode, it transitions high with the first nibble of preamble and is pull ed low when the last data nibble has been received. in 10base-t mode, it tran sitions high when the start-of-frame delimiter (sfd) is detected. this pin is tristated in isolate mode. rxd[3:0] 19-22 coz receive data: received data is prov ided to the mac via rxd[3:0]. these pins are tristated in isolate mode.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 7 - rev_1.1 mii (continued) name pin type description rx_er 25 coz receive error: rx_er is asserted high when an error is detected during frame reception. in pcs bypass mode, th is pin becomes the msb of the receive 5-bit code group. this pin is tristated in isolate mode. mdc 18 cis management data clock: mdc is the clock used for transferring data via the mdio pin. mdio 17 cio management data input/output: mdio is a bi-directional port used to access management registers within th e 78Q2120C. this pin requires an external pull-up resistor as specified in ieee-802.3. phy address name pin type description phyad[4:0] 12-16 ci phy address: allows 31 configur able phy addresses. the 78Q2120C always responds to data transactions via the mii interface when the phyad bits are all zero independent of the logic levels of the phyad pins. pma (physical media attachment) interface name pin type description pcsbp 64 cid pcs bypass: when high, the 100base-tx pcs is bypassed, as well as the scrambler and descrambler functions. scrambled 5-bit code groups for transmission are applied to the tx_e r, txd[3:0] pins and received on the rx_er, rxd[3:0] pins. the rx_dv a nd tx_en signals are not valid in this mode. pcs bypass mode is only va lid when 100base-tx is enabled and auto-negotiate disabled. this mode can also be entered with mr16.1. control and status name pin type description rst 6 ciu active-low reset: when pu lled low, the pin resets the chip. the reset pulse must be long enough to guarantee stabilization of the supply voltage and startup of the oscillator. there are 2 other ways to reset the chip: i) through the internal power-on-reset (activated when the chip is being powered up) ii) through the mii register bit (mr0.15) pwrdn 7 cid power-down: the 78Q2120C may be placed in a low power consumption state by setting this signal to logic high. while in power-down state, the 78Q2120C still responds to management transactions. the same power- down state can also be activated throu gh the pwrdn bit in the mii register (mr0.11).
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 8 - rev_1.1 control and status (continued) name pin type description iso 2 ci isolate: when set to logic one, the 78Q2120C will present a high impedance on its mii output pins. this allows for multiple chips to be attached to the same mii interface. when the 78Q2120C is isolated, it still responds to management transactions. the same high impedance state can also be achieved through the iso bit in the mii register (mr0.10). isodef 1 ci isolate default: this pin determines the power-up/reset default of the iso bit (mr0.10). if it is connected to supply, the iso bit will have a default value of ?1?. otherwise, the bit defaults to ?0?. when this signal is tied to supply, it allows multiple chips to be connected to the same mii interface. anega 47 ci auto-negotiation ability: strapped to logic high to allow auto- negotiation function. when strapped to logic low, auto-negotiation logic is disabled and manual technology selection is done through tech[2:0] pins. this pin is reflected as the anega bit in mr1.3. tech[2:0] 44-46 ci technology ability/selec t: tech[2:0] sets t he technology ability of the chip which is reflected in mr0.13,8, mr1.14:11 and mr4.12:5. tech[2:0] technology ability 111 both 10base-t and 100base-tx, both half and full duplex 001 10base-t, half duplex 010 100base-tx, half duplex 011 both 10base-t and 100base-tx, half duplex 100 none 101 10base-t both half and full duplex 110 100base-tx both half and full duplex rptr 50 cid repeater mode: when pulled high, this pin puts the chip into repeater mode. in this mode, full duplex is proh ibited, crs responds to receive activity only and, in 10base-t mode, the sqe test function is disabled. this mode can also be entered with mr16.15 mdi (media dependent interface) name pin type description txop/n 61,62 a transmit output positive/negative: transmitter differential outputs for both 10base-t and 100base-tx operation. rxip/n 52,51 a receive input positive/negative: receiver differential inputs for both 10base-t and 100base-tx operation.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 9 - rev_1.1 led indicators the led pins use standard logic drivers. they output a logic low when the led is meant to be on and a logic high when it is meant to be off. the led should be c onnected in series with a resi stor between the output pin and the power supply. name pin type description ledl 40 co led link: on for link up. ledtx 39 co led transmit: on when there is a transmission (normally off). ledrx 38 co led receive: on when ther e is a reception (normally off). ledcol 37 co led collision: in half duplex mode, this is a collision indicator and turns on when a collision occurs. in full duplex mode, this led is held off. ledbtx 36 co led 100base-tx: on for 100base-t x connection and off for other connections. ledbtx is off during auto-negotiation. ledbt 48 co led 10base-t: on for 10base-t co nnection and off for other connections. ledbt is off during auto-negotiation. ledfdx 49 co led full duplex: on when in full duplex mode and off when in half duplex mode. oscillator/clock name pin type description ckin 4 cis clock input: connects to a 25 mhz clock source. this pin should be held low when xtlp and xtln are being used as the 25 mhz clock source. xtlp/n 59,58 a crystal pins: should be connected to a 25 mhz crystal. when ckin is being used as the 25 mhz clock source , these pins should be left floating or connected together. miscellaneous pin name pin type description intr 35 coz interrupt pin: this pin is used to signal an interrupt to the media access controller. the pin is held in the hi gh impedance state when an interrupt is not indicated. the pin will be forced high or low to signal an interrupt depending upon the value of the intr_level bit (mr16.14). the events which trigger an interrupt can be programmed via the interrupt control register located at address mr17. nc 54,56 -- no connect. do not connect to ground or supply. power supply and ground name pin type description vcc 8,11,41, 43,57,63 s 3.3v supply gnd 3,5,9,10, 42,53,55,60 g ground
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 10 - rev_1.1 register description the 78Q2120C implements 11 16-bit registers, which are accessible via the mdio and mdc pins. the supported registers are shown below in the following table. attemp ts to read unsupported registers will be ignored and the mdio pin will not be enabled as an output, as per the ieee 802.3 specification. all of t he registers except those, which are unique to the 78Q2120C, will respond to the broadca st phyad value of ?00000?. the registers specific to the 78Q2120C occupy address space mr16-22. address symbol name default (hex) 0 mr0 control (3100) 1 mr1 status (7809) 2 mr2 phy identifier 1 000e 3 mr3 phy identifier 2 70c5 4 mr4 auto-negotiation advertisement (01e1) 5 mr5 auto-negotiation link partner ability 0000 6 mr6 auto-negotiation expansion 0000 7 mr7 not implemented 0000 8-14 mr8-14 reserved 0000 15 mr15 not implemented 0000 16 mr16 vendor specific (0140) 17 mr17 interrupt control/status register 0000 18 mr18 diagnostic register/test register 0000 19 mr19 transceiver control 4xxx legend: type description type description r readable by management. w writeable by management. sc writeable by management. self clearing. rc readable by management. cleared upon a read operation. 0/1 default value upon power up or reset (0/1) default value dependent on pin settings. the value in bracket indicates typical case.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 11 - rev_1.1 mr0: control register bit symbol type default description 0.15 reset r/sc 0 reset: setting this bit to ?1? resets the device and sets all registers to their default states. this bit is self-clearing. 0.14 loopbk r/w 0 loopback: when this bit is set to ?1?, no transmission of data on the network medium occurs and any re ceive data on the network medium is ignored. by default, the loopba ck signal path will encompass as much of the 78Q2120C circuitry as possible. 0.13 speedsl r/w (1) speed selection: this bit determi nes the speed of operation of the 78Q2120C. setting this bit to ?1? indicates 100base-tx operation and a ?0? indicates 10base-t mode. this bit will default to a ?1? upon reset. if the tech[2:0] pins are all logic zero and auto-negotiation is not enabled, this bit will be writeable. if auto-negotiation is not enabled and the tech[2:0] pins are set to indicate that only 10base-t is supported, this bit will be forced to logic zero and will not be writeable. if auto-negotiation is not enabled and the tech[2:0] pins are set to indicate that only 100base-tx is supported, this bit will be forced to logic one and will not be writeable. when auto-negotiation is enabled, this bit will not be writeable and will have no effect on the 78Q2120C. if the tech[2:0] pins are brought to zero from another value, this bit will retain its original valu e until it is overwritten. 0.12 anegen r/w (1) auto-negotiation enable: setting this bit to ?1? shall enable the auto- negotiation process. this bit can only be set if the anega pin is a logic one and will default to ?1? upon reset in this case. if this bit is cleared to ?0?, manual speed and duplex mode selection is accomplished through bits 0.13 ( speedsl ) and 0.8 ( duplex ) of the control register or the tech[2:0] pi ns according to the table shown in the section describing the te ch[2:0] pins. if the anega pin is brought from ?0? to ?1? and reset is not asserted, this bit will remain at ?0? until a ?1? is written. 0.11 pwrdn r/w 0 power-down: the device may be placed in a low power consumption state by setting this bit to ?1?. wh ile in power-down state, the device will still respond to mana gement transactions. setting the pwrdn pin high can also activate the power-down state. 0.10 iso r/w (0) isolate: when set to ?1?, the device will present a high-impedance on its mii output pins. this allows fo r multiple phy?s to be attached to the same mii interface. when the devic e is isolated, it still responds to management transactions. the default value of this bit depends on the isodef pin. when isodef pin is tied high, the iso bit defaults to high. otherwise, it defaults to low. the isolate mode can also be activated through the iso pin. 0.9 raneg r/sc 0 restart auto-negotiation: normally, the auto-negotiation process is started at power up. the process can be restarted by setting this bit to ?1?. this bit is self-clearing.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 12 - rev_1.1 mr0: control register (continued) bit symbol type default description 0.8 duplex r/w (1) duplex mode: this bit determines whether the device supports full- duplex or half-duplex. a ?1? indicates full-duplex operation and a ?0? indicates half-duplex. this bit will default to ?0? upon reset, if the tech[2:0] pins are all logic zero and auto-negotiation is not enabled, this bit will be writeable. if auto-negotiation is not enabled and the tech[2:0] pins are set to indicate that only full-duplex is supported, this bit will be forced to ?1? and will not be writeable. if auto-negotiation is not enabled and the tech[2:0] pins are set to indicate that only half-duplex is supported, this bit will be forced to ?0? and will not be writeable. when auto-negotiation is enabled, this bit will not be writeable and will have no effect on t he device. if the tech[2:0] pins are brought to zero from another value, this bit will retain its original value until it is overwritten. 0.7 colt r/w 0 collision test: when this bit is set to ?1?, the device will assert the col signal in response to the as sertion of the tx_en signal. collision test is disabled if the pc sbp pin is high. collision test can be activated regardless of t he duplex mode of operation. 0.6:0 rsvd r 0 reserved mr1: status register bits 1.15 through 1.11 reflect the ability of the 78Q2120C as configured by the tech[2:0] pins. they do not reflect any ability changes made via the mii management interface to bits 0.13 ( speedsl ) , 0.12 ( anegen ) and 0.8 ( duplex ). bit symbol type default description 1.15 100t4 r 0 100base-t4 ability: reads ?0 ? to indicate the 78Q2120C does not support 100base-t4 mode. 1.14 100x_f r (1) 100base-tx full duplex ability: 0 : not able 1 : able 1.13 100x_h r (1) 100base-tx half duplex ability: 0 : not able 1 : able 1.12 10t_f r (1) 10base-t full duplex ability: 0 : not able 1 : able 1.11 10t_h r (1) 10base-t half duplex ability: 0 : not able 1 : able 1.10 100t2_f r 0 100base-t2 full duplex ability: reads ?0? to i ndicate the 78Q2120C does not support 100base-t2 full duplex mode.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 13 - rev_1.1 mr1: status register bit symbol type default description 1.9 100t2_h r 0 100base-t2 half duplex ability: reads ?0? to indi cate the 78Q2120C does not support 100base-t2 full duplex mode. 1.8 exts r 0 extended status information ava ilability: reads ?0? to indicate the 78Q2120C does not support extended status information on mr15. 1.7 rsvd r 0 reserved 1.6 mfps r 0 management frame preamble suppression support: a ?0? indicates that the 78Q2120C can read management frames with a preamble. 1.5 anegc r 0 auto-negotiation complete: a logic one indicates that the auto- negotiation process has been comple ted, and that the contents of registers mr4,5,6 are valid. 1.4 rfault rc 0 remote fault: a logic one indicates that a remote fault condition has been detected and when so, it remains set until it is cleared. this bit can only be cleared by reading this register (mr1) via the management interface. 1.3 anega r (1) auto-negotiation ability: when set, this bit indicates the device?s ability to perform auto-negotiation. the value of this bit is determined by the anegen bit (mr0.12). 1.2 link r 0 link status: a logic one indicates that a valid link has been established. if the link status should transition from an ok status to a not-ok status, this bit will become cleared and remains cleared until it is read. 1.1 jab rc 0 jabber detect: in 10base- t mode, this bit is set during a jabber event. after a jabber event, the bi t remains set until cleared by a read operation. 1.0 extd r 1 extended capability: reads ?1? to indicate the 78Q2120C provides an extended register set (mr2 and beyond).
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 14 - rev_1.1 mr2: phy identifier register 1 bit symbol type value description 2.15:0 oui [23:6] r 000eh organizationally unique identifier: this value is 00-c0-39 for tdk semiconductor corporation. this regi ster contains the first 16-bits of the identifier. mr3: phy identifier register 2 bit symbol type value description 3.15:10 oui [5:0] r 1ch organizationally unique identifier: remaining 6 bits of the oui. 3.9:4 mn r 0ch model number: the last 2 digits of the model number 2120c are encoded into the 6 bits. 3.3:0 rn r 5h revision number: the value ?0101? corresponds to the fifth revision of the silicon. mr4: auto-negotiation advertisement register bit symbol type default description 4.15 np r 0 next page: not supported. reads logic zero. 4.14 rsvd r 0 reserved 4.13 rf r/w 0 remote fault: setting this bit to ?1? allows the device to indicate to the link partner a remote fault condition. 4.12:5 taf r/w (0fh) technology ability field: the default value of this field is dependent upon the mr1.15:11 register bits. this field can be overwritten by management to auto-negotiate to an alternate common technology. writing to this register has no effect until auto-negotiation is re-initiated. 4.12:10 a7:5 r 0 reserved for future technology. 4.9 a4 r 0 100base-t4: the 78Q2120C does not support 100base-t4 operation. 4.8 a3 r/w (1) 100base-tx full duplex: if the mr1.14 bi t is ?1?, this bit will be set to ?1? upon reset and will be writeable. otherwise, this bit cannot be set to ?1? by the management. 4.7 a2 r/w (1) 100base-tx: if the mr1.13 bit is ?1?, this bit will be set to ?1? upon reset and will be writeable. otherwise, this bit cannot be set to ?1? by the management. 4.6 a1 r/w (1) 10base-t full duplex: if the mr1.12 bit is ?1?, this bit will be set to ?1? upon reset and will be writeable. otherwise, this bit cannot be set to ?1? by the management. 4.5 a0 r/w (1) 10base-t: if the mr1.11 bit is ?1?, this bit will be set to ?1? upon reset and will be writeable. otherwise, this bit cannot be set to ?1? by the management. 4.4:0 s4:0 r 01h selector field: hard coded with the value of ?00001? for ieee 802.3.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 15 - rev_1.1 mr5: auto-negotiation link partner ability register bit symbol type default description 5.15 np r 0 next page: when ?1? is read, it indicates the link partner wishes to engage in next page exchange. 5.14 ack r 0 acknowledge: when ?1? is read, it indicates the link partner has successfully received at least 3 consecutive and consistent flp bursts. 5.13 rf r 0 remote fault: when ?1? is read, it indicates the link partner has a fault. 5.12:5 a7:0 r 0 technology ability field: this field contains the technology ability of the link partner. the bit definit ion is the same as mr4.12:5. 5.4:0 s4:0 r 00h selector field: this field contains the type of message sent by the link partner. for ieee 802.3 compliant link partner, this field should be ?00001?. mr6: auto-negotiation expansion register bit symbol type default description 6.15:5 rsvd r 0 reserved 6.4 pdf rc 0 parallel detection fault: when ?1? is read, it indicates that more than one technology has been detected during link up. this bit is cleared when read. 6.3 lpnpa r 0 link partner next page able: when ?1? is read, it indicates the link partner supports the next page function. 6.2 npa r 0 next page able: reads ?0? since the 78Q2120C does not support next page function. 6.1 prx rc 0 page received: reads ?1? when a new link code word has been received into the auto-negotiation link partner ability register. this bit is cleared upon read. 6.0 lpanega r 0 link partner auto-negotiation able: when ?1? is read, it indicates the link partner is able to participate in the auto-negotiation function.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 16 - rev_1.1 mr16: vendor specific register bit symbol type default description 16.15 rptr r/w (0) repeater mode: when set, the 78Q2120C is put into repeater mode of operation. in this mode, full dupl ex is prohibited, crs responds to receive activity only and, in 10base- t mode, the sqe test function is disabled. 16.14 inpol r/w 0 when this bit is ?0?, the intr pin is forced low to signal an interrupt. setting this bit to ?1? causes the intr pin to be forced high to signal an interrupt. 16.13 rsvd r 0 reserved 16.12 txhim r/w 0 transmitter high-impedance mode: when set, the txop/txon transmit pins and the tx_clk pin are put into a high-impedance state. the receive circuitry remains fully functional. 16.11 sqei r/w 0 sqe test inhibit: setting this bit to ?1? disables 10base-t sqe testing. by default, this bit is ?0? and the sqe test is performed by generating a col pulse following the completion of a packet transmission. 16.10 nl10 r/w 0 10base-t natural loopback: setting this bit to ?1? causes transmit data received on the txd0-3 pins to be automatically looped back to the rxd[0:3] pins when 10base-t mode is enabled. 16.9 rsvd r/w 0 reserved 16.8 rsvd r/w 1 reserved 16.7 rsvd r/w 0 reserved 16.6 rsvd r/w 1 reserved 16.5 apol r/w 0 auto polarity: during auto-n egotiation and 10base-t mode, the 78Q2120C is able to automatically invert the received signal due to a wrong polarity connection. it does so by detecting the polarity of the link pulses. setting this bit to ?1? disables this feature. 16.4 rvspol r/w 0 reverse polarity: the reverse polarity is detected either through 8 inverted 10base-t link pulses (nlp) or through one burst of inverted clock pulses in the auto-negotiation link pulses (flp). when the reverse polarity is detected and if the auto polarity feature is enabled, the 78Q2120C will invert the receive data input and set this bit to ?1?. if auto polarity is disabled, then this bit is writeable. writing a ?1? to this bit forces the polarity of the receive signal to be reversed. 16.3:2 rsvd r/w 0h reserved: must set to ?00?.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 17 - rev_1.1 mr16: vendor specific register (continued) bit symbol type default description 16.1 pcsbp r/w (0) pcs bypass mode: when set, the 100base-tx pcs and scrambling/ descrambling functions are bypassed. scrambled 5-bit code groups for transmission are applied to the tx_e r, txd[3:0] pins and received on the rx_er, rxd[3:0] pins. th e rx_dv and tx_en signals are not valid in this mode. pcsbp mode is valid only when 100base-tx mode is enabled and auto-negotiate disabeled. 16.0 rxcc r/w 0 receive clock control: this function is valid only in 100base-tx mode. when set to ?1?, the rx_clk signal will be held low when there is no data being received (to save power). the rx_clk signal will restart 1 clock cycle before the asse rtion of rx_dv and be shut off 64 clock cycles after rx_dv goes low. rxcc is disabled when loopback mode is enabled (mr0.14 is high). this bit should be kept at logic zero when pcs bypass mode is used. mr17: interrupt control/status register the interrupt control/status register provides the means for controlling a nd observing the events, which trigger an interrupt on the intr pin. this register can also be used in a polling mo de via the mii serial interface as a means to observe key events within the phy via one register address. bits 0 through 7 are status bits, which are each set to logic one based upon an event. these bits are cl eared after the register is read. bits 8 through 15 of this register, when set to logic one, enable their correspon ding bit in the lower byte to signal an interrupt on the intr pin. the level of this interrupt can be set via the mr16.14 ( inpol ) bit. bit symbol type default description 17.15 jabber_ie r/w 0 jabber interrupt enable 17.14 rxer_ie r/w 0 receive error interrupt enable 17.13 prx_ie r/w 0 page received interrupt enable 17.12 pdf_ie r/w 0 parallel detect fault interrupt enable 17.11 lp-ack_ie r/w 0 link partner acknowledge interrupt enable 17.10 ls_chg_ie r/w 0 link status change interrupt enable 17.9 rfault_ie r/w 0 remote fault interrupt enable 17.8 aneg- comp_ie r/w 0 auto-negotiation complete interrupt enable 17.7 jab_int rc 0 jabber interrupt: this bit is set high when a jabber event is detected by the 10base-t circuitry. 17.6 rxer_int rc 0 receive error interrupt: this bit is set high when the rx_er signal transitions high. 17.5 prx_int rc 0 page received interrupt: this bit is set high when a new page has been received from the link partner during auto-negotiation. 17.4 pdf_int rc 0 parallel detect fault interrupt: th is bit is set high by the auto- negotiation logic when a parallel detect fault condition is indicated.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 18 - rev_1.1 mr17: interrupt control/status register (continued) bit symbol type default description 17.3 lp-ack_int rc 0 link partner acknowledge interrupt: this bit is set high by the auto-negotiation logic when flp bursts are received with the acknowledge bit set. 17.2 ls_chg_int rc 0 link status change interrupt: this bit is set when the link transitions from an ok status to a fail status. 17.1 rfault_int rc 0 remote fault interrupt: this bit is set when a remote fault condition has been indicated by the link partner. 17.0 aneg- comp_int rc 0 auto-negotiation complete interrupt: this bit is set by the auto- negotiation logic upon successful completion of auto-negotiation. mr18: diagnostic register bit symbol type default description 18.15 rsvd r 0 reserved 18.14:13 rsvd r/w 00h reserved: must set to ?00h?. 18.12 anegf rc 0 auto-negotiation fail indication: this bit is set when auto- negotiation completes and no common technology was found. it remains set until read. 18.11 dplx r 0 duplex indication: this bit indicates the result of the auto- negotiation for duplex arbitration as follows: 0 : half-duplex was the highest common denominator 1 : full-duplex was the highest common denominator 18.10 rate r 0 rate indication: this bit indicates the result of the auto-negotiation for data rate arbitration as follows: 0 : 10base-t was the highest common denominator 1 : 100base-tx was the highest common denominator 18.9 rx_pass r 0 receiver pass indication: in 10base-t mode, this bit indicates that manchester data has been detected. in 100base-tx mode, it indicates that the receive signal activity has been detected (but not necessarily locked on to). 18.8 rx_lock r 0 receive pll lock indication: indi cates that the receive pll has locked onto the receive signal for 100base-tx operation. 18.7:0 rsvd r/w 00h reserved: must set to ?00h?.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 19 - rev_1.1 mr19: transceiver control bit symbol type default description 19.15:14 rsvd r/w 01 reserved 19.13:12 rsvd r/w 00 reserved 19.11:10 txo[1:0] r/w 01 transmit amplitude selection: sets the transmit output amplitude to account for transmit transformer insertion loss. 00 : gain set for 0.0db of insertion loss 01 : gain set for 0.4db of insertion loss 10 : gain set for 0.8db of insertion loss 11 : gain set for 1.2db of insertion loss 19.9:0 rsvd r xxxh reserved mr20: reserved bit symbol type default description 20.15:0 reserved na 0000h reserved: must be 0000h. mr21: reserved bit symbol type default description 21.15:0 reserved na 0000h reserved: must be 0000h. mr22: reserved bit symbol type default description 22.15:0 reserved na 0000h reserved: must be 0000h.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 20 - rev_1.1 electrical specifications absolute maximum ratings operation above maximum rating may permanently damage the device. parameter rating dc supply voltage (vcc) -0.5 to 4.0 vdc storage temperature -65 to 150 c pin voltage (cmos inputs) -0.3 to 5.5 vdc pin voltage (cmos outputs except txop/n) -0.3 to (vcc+0.6) vdc pin voltage (txop/n only) -0.3 to (vcc+1.4) vdc pin current 120 ma recommended operating conditions unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges: parameter rating dc voltage supply (vcc) 3.3 0.3 vdc ambient operating temperature (ta) 0 to +70 c dc charateristics: parameter symbol conditions min nom max unit supply current i cc vcc = 3.3v; auto-negotiation 10bt (idle) 10bt (normal activity) 100btx 40 26 88 88 48 32 110 110 ma supply current i cc power-down mode 5 ma digital i/o characteristics: pins of type ci, ciu, cid, cio: parameter symbol conditions min nom max unit input voltage low vil 0.8 v input voltage high vih 2.0 v input current iil, iih -1 1 a pull-up resistance rpu type ciu only 38 56 78 k ? pull-down resistance rpd type cid only 38 56 78 k ? input capacitance cin 8 pf
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 21 - rev_1.1 pins of type cis: parameter symbol conditions min nom max unit low-to-high threshold vt+ 1.3 1.7 v high-to-low threshold vt- 0.80 1.20 v input current iil, iih -1 1 a input capacitance cin 8 pf pins of type co, coz, cio: parameter symbol conditions min nom max unit output voltage low vol iol = 8ma 0.4 v output voltage high voh ioh = -8ma 2.4 v output transition time tt c l = 20pf 6 ns tristate output leakage current iz type coz only -1 1 a digital timing characteristics mii transmit interface characteristics symbol conditions min nom max unit setup time: tx_clk to txd[3:0], tx_en, tx_er tx su 15 ns hold time: tx_clk to txd[3:0], tx_en, tx_er tx hd 0 ns ckin-to-tx_clk delay t ckin 0 40 ns tx_clk duty-cycle 40 60 % transmit inputs to the 78Q2120C ckin tx_clk txd[3:0] tx_en or tx_er t ckin tx su tx hd
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 22 - rev_1.1 mii receive interface characteristics symbol conditions min nom max unit receive output delay: rx_clk to rxd[3:0], rx_dv, rx_er rx dly 10 30 ns rx_clk duty-cycle 40 60 % receive outputs from the 78Q2120C mdio interface input timing characteristics symbol conditions min nom max unit setup time: mdc to mdio mio su 10 ns hold time: mdc to mdio mio hd 0 ns max frequency: mdc f max 25 mhz mdio as an input to the 78Q2120C rx dly (max) rx dly (min) rx_clk rxd[3:0] rx_dv or rx_er mdc mdio mio su mio hd
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 23 - rev_1.1 mdio interface output timing characteristics symbol conditions min nom max unit mdc to mdio data delay mc2d 30 ns mdio output from high z to driven after mdc mcz2d 30 ns mdio output from driven to high z after mdc mcd2z 30 ns mdio as an output from the 78Q2120C mdc mdio mcz2d mc2d mcd2z
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 24 - rev_1.1 mdio interface output timing z preamble phy address read write data turnaround start of frame operation code 1 1 1 0 1 1 0a aaaarrrrrz 0 dddddddddddddddd z z preamble phy address data turnaround start of frame operation code 1 1 1 0 1 0 1a aaaarrrrr 1 0 dddddddddddddddd z
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 25 - rev_1.1 100base-tx system timing system timing requirements for 100base-tx operation ar e listed in table 24-2 of clause 24 of ieee 802.3. parameter condition nom unit tx_en sampled to first bit of ?j? on mdi output 12 bt first bit of ?j? on mdi input to crs assert 15 bt first bit of ?t? on mdi input to crs de-assert 23 bt first bit of ?j? on mdi input to col assert 16 bt first bit of ?t? on mdi input to col de-assert 24 bt tx_en sampled to crs assert rptr = low 4 bt tx_en sampled to crs de-assert rptr = low 4 bt 10base-t system timing parameter condition min nom max unit tx_en (mii) to td delay 6 bt rd to rxd at (mii) delay 6 bt collision delay 9 bt sqe test wait 1 s sqe test duration 1 s jabber on-time* 20 150 ms jabber off-time* 250 750 ms * guarantee by design. the specifications in the following table are included for information only.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 26 - rev_1.1 analog electrical characteristics 100base-tx transmitter parameter condition min nom max unit peak output amplitude (|vp+|, |vp-|) (see note below) best-fit over 14 bit times; 0.5 db transformer loss 950 1050 mvpk output amplitude symmetry | vp +| | vp -| 0.98 1.02 output overshoot percent of vp+, vp- 5 % rise/fall time (tr, tf) 10-90% of vp+, vp- 3 5 ns rise/fall time imbalance | tr - tf | 500 ps duty cycle distortion deviation from best-fit time-grid; 010101... sequence 250 ps jitter scrambled idle 1.4 ns note: measured at the line side of the transformer. test condition: transformer p/n: tla-6t103 line termination: 100 ? 1% 100base-tx transmitter (informative) the specifications in the following table are included for information only. they are mainly a function of the external transformer and termination resistors used for measurements. parameter condition min max unit return loss 2 < f < 30 mhz 30 < f < 60 mhz 60 < f < 80 mhz 16 16 20 30 ? ? ? ? ? ? ? log f mhz 10 db open-circuit inductance -8 < iin < 8 ma 350 h
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 27 - rev_1.1 100base-tx receiver parameter condition min nom max unit signal detect assertion threshold 600 750 900 mvppd signal detect de-assertion threshold 300 400 500 mvppd differential input resistance 20 k ? jitter tolerance (pk-pk) 4 ns baseline wander tracking -75 +75 % signal detect assertion time not tested 1000 s signal detect de-assertion time not tested 2 s 10base-t transmitter the manchester-encoded data pulses, t he link pulse and the start-of-idle puls e are tested against the templates and using the procedures found in clause 14 of ieee 802.3. parameter condition min nom max unit peak differential output signal (see note below) all data patterns 2.2 2.8 v harmonic content (db below fundamental) all ones data not tested 27 db link pulse width 100 ns start-of-idle pulse width last bit 0 last bit 1 300 350 ns ns note: measured at the line side of the transformer. test condition: transformer p/n: tla-6t103 line termination: 100 ? 1%
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 28 - rev_1.1 10base-t transmitter (informative) the specifications in the following table are included for information only. they are mainly a function of the external transformer and termination resistors used for measurements. parameter condition min nom max unit output return loss 15 db output impedance balance 1 mhz < freq < 20 mhz 29 17 10 ? ? ? ? ? ? ? log f db peak common-mode output voltage 50 mv common-mode rejection 15 v pk , 10.1 mhz sine wave applied to transmitter common- mode. all data sequences. 100 mv common-mode rejection jitter 15 v pk , 10.1 mhz sine wave applied to transmitter common- mode. all data sequences. 1 ns 10base-t receiver parameter condition min nom max unit dll phase acquisition time 10 bt jitter tolerance (pk-pk) 30 ns input squelched threshold 600 750 900 mvppd input unsquelched threshold 300 400 500 mvppd differential input resistance 20 k ? bit error ratio 10 -10 common-mode rejection square wave 0 < f < 500 khz not tested 25 v
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 29 - rev_1.1 figure 1: typical applications circuit 50 ohm impedance traces gnd c4 0.1 crs reset r15 75 interupt r7 33 rxd3 r6 33 c1 0.1 txd0 c6 0.1 rxd0 68 ohm impedance traces txd3 mdc gnd c10 27pf r3 49.9 1% 0603 c12 0.1 txclk r14 75 r1 2k c7 0.01 ledfd r17 75 r11 33 note 1 led10 j1 rj45 1 2 3 4 5 6 7 8 9 10 c9 27pf r12 33 ledtx 1) recommend to leave pins 56 and 56 as nc for 78Q2120C device. connecting a resistor between these pins as in the 78q2120 will have no effect on this device r18 75 r5 49.9 1% 0603 c11 0.01 1.5kv 1808 rxer rxd1 txen txd1 r8 33 led100 vcc 50 ohm impedance traces txer r4 49.9 1% 0603 rxr vcc gnd r9 33 c2 0.1 ledrx ledl r10 33 gnd vcc vcc rxd2 col gnd r16 75 rxclk txd2 y1 25.000mhz 50ppm r2 49.9 1% 0603 rxdv c8 0.01 vcc ledcol mdio gnd c3 0.1 r13 75 gnd c5 0.1 cgnd t1 tla-6t118lf tdk smt16 6 8 7 4 10 9 11 5 15 16 14 12 13 2 3 1 rd+ rd- rdct nc1 rxct rx- rx+ nc2 txct tx+ tx- nc3 nc4 tdct td- td+ gnd gnd u1 78Q2120C-64cgt tsc lqfp64 28 27 32 31 30 29 24 19 20 21 22 64 63 4 6 59 58 53 10 43 11 52 51 56 54 62 61 41 60 55 18 33 23 17 34 9 8 26 25 7 47 44 45 46 49 48 50 57 40 39 38 37 36 12 13 14 15 16 5 3 35 42 2 1 txen txclk txd3 txd2 txd1 txd0 rxclk rxd3 rxd2 rxd1 rxd0 pcsbp vcc ckin rst xtlp xtln gnd gnd vcc vcc rxip rxin nc nc txon txop vcc gnd gnd mdc col rxdv mdio crs gnd vcc txer rxer pwrdn anega tech2 tech1 tech0 ledfdx ledbt rptr vcc ledl ledtx ledrx ledcol ledbtx phyad4 phyad3 phyad2 phyad1 phyad0 gnd gnd intr gnd iso isodef
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 30 - rev_1.1 isolation transformers two simple 1:1 isolation transformers are all that are required at the line interface, but transformers with integrated common-mode choke are recommended for ex ceeding fcc requirements. this table gives the recommended line transfor mer characteristics: name value condition turns ratio 1 ct : 1 ct 5% open-circuit inductance 350 h (min) @ 10 mv, 10 khz leakage inductance 0.40 h (max) @ 1 mhz (min) inter-winding capacitance 12 pf (max) d.c. resistance 0.9 ? (max) insertion loss 0.4 db (typ) 0 - 65 mhz hipot 1500 vrms note: the 100base-tx amplitude specifications assume a transformer loss of 0.4 db. for the transmit line transformer with higher insertion losses, up to 1.2 db of insertion loss can be compensated by selecting the appropriate setting in the transmit amplitude selection bits in register mr19.11:10. reference crystal if the internal crystal oscillator is to be used, a crys tal with the following characteristics should be chosen: name value units frequency 25.00000 mhz load capacitance* 4** pf frequency tolerance 50 ppm aging 2 ppm/yr temperature stability ( 0 - 70 o c) 5 ppm oscillation mode parallel resonance, fundamental mode parameters at 25 o c 2 o c ; drive level = 0.5 mw shunt capacitance (max) 8 pf motional capacitance (min) 10 f f series resistance (max) 60 ? spurious response (max) > 5 db below main within 500 khz * equivalent differential capacitance across the xtlp/xtln pins. ** if crystal with a larger load is used, external shunt capacitors to ground should be added to make up the equivalent capacitance difference.
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 31 - rev_1.1 package pin designations (top view) txd0 txd1 tx_ en tx_clk tx_ er rx_ er rx_ clk txd3 txd2 rxd1 rxd2 rxd3 mdc mdio rxd0 rx_ dv tdk 78Q2120C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 63 62 61 60 59 58 57 56 55 54 53 52 51 64 phya d1 phya d3 vcc gnd pwrdn gnd gnd phya d2 phya d0 phya d4 gnd vcc rst cki n iso isodef ledl ledbt anega tech0 tech1 tech2 vcc gnd vcc ledtx ledcol ledbtx int r crs col ledrx gnd gnd txon vcc pcsbp txop ledfdx rpt r rxi n rxip vcc nc xt ln xt lp nc gnd txd0 txd1 tx_ en tx_clk tx_ er rx_ er rx_ clk txd3 txd2 rxd1 rxd2 rxd3 mdc mdio rxd0 rx_ dv txd0 txd1 tx_ en tx_clk tx_ er rx_ er rx_ clk txd3 txd2 rxd1 rxd2 rxd3 mdc mdio rxd0 rx_ dv tdk 78Q2120C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 63 62 61 60 59 58 57 56 55 54 53 52 51 64 tdk 78Q2120C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 63 62 61 60 59 58 57 56 55 54 53 52 51 64 49 50 63 62 61 60 59 58 57 56 55 54 53 52 51 64 phya d1 phya d3 vcc gnd pwrdn gnd gnd phya d2 phya d0 phya d4 gnd vcc rst cki n iso isodef phya d1 phya d3 vcc gnd pwrdn gnd gnd phya d2 phya d0 phya d4 gnd vcc rst cki n iso isodef ledl ledbt anega tech0 tech1 tech2 vcc gnd vcc ledtx ledcol ledbtx int r crs col ledrx ledl ledbt anega tech0 tech1 tech2 vcc gnd vcc ledtx ledcol ledbtx int r crs col ledrx gnd gnd txon vcc pcsbp txop ledfdx rpt r rxi n rxip vcc nc xt ln xt lp nc gnd gnd gnd txon vcc pcsbp txop ledfdx rpt r rxi n rxip vcc nc xt ln xt lp nc gnd
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 32 - rev_1.1 mechanical specifications 64-lqfp 11.7 (0.460) 12.3 (0.484) 0.60 (0.024) typ. 1.40 (0.055) 1.60 (0.063) 11.7 (0.460) 12.3 (0.484) 0.00 (0) 0.20 (0.008) 9.8 (0.386) 10.2 (0.402) 0.50 (0.0197) typ. 0.14 (0.006) 0.28 (0.011) pin no. 1 indicator +
78Q2120C 10/100base-tx transceiver ? 2003 tdk semiconductor corporation, proprietary and confidential - 33 - rev_1.1 ordering information part description order number package mark 78Q2120C 64-pin plastic lqfp 78Q2120C-64cgt 78Q2120C-64t 78Q2120C 64-pin plastic lqfp-lead free 78Q2120C-64cgt/f 78Q2120C-64t no responsibility is assumed by tdk semiconductor corporation for use of this product or for any infringements of patents and trademarks or other rights of third parties resulting from it s use. no license is granted under any patents, patent rights or trademarks of tdk se miconductor corporation, and the company reserves the right to make changes in specifications at any time wit hout notice. accordingly, the r eader is cautioned to verify that the data sheet is current before placing orders. tdk semiconductor corporation, 6440 oak canyon rd., irvi ne, ca 92618-5201, (714) 508-8800, fax: (714) 508-8877

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